In the prior art, it is known that LSI semiconductor memories may provide erroneous data upon read out of the information stored therein. Such errors in the read data may be occasioned by defective memory cells in which the defective memory cell unconditionally provides, as an output therefrom, a signal indicative of the storage of a e.g., 0, therein, while, alternatively, such errors in the read data may be random errors due to electronic perturbations during write in or read out. Accordingly, many techniques have been devised by electronic data processing engineers to overcome the effect of errors in read data upon the operation of the associated data processing system, and, particularly the LSI memory with which the errors are associated. In the J. L. Brown, et al, U.S. Pat. No. 3,800,286, there is disclosed a system wherein a CAM is searched for an address. If the address is not available in the CAM, the main memory is referenced; if the address is available in the CAM, the CAM associated buffer memory is referenced. In the J. A. Weisbecker, U.S. Pat. No. 3,234,521, there is disclosed a system wherein a CAM is searched for an address. If the address is stored in the CAM, indicating a defective address in main memory, the CAM produces a substitute address in main memory that is then referenced in main memory. Also there is provided a change in regular main memory timing to allow for the additional time required to reference the main memory at the substitute address. Still further, in the H. A. Perkins, Jr., U.S. Pat. No. 3,331,058, there is disclosed a memory with regular data positions and stored data positions, which substitute for defective regular data positions, that is utilized by an address decoder to store data in a stored data position at the address of the regular data position that is defective. The present invention is considered to be an improvement invention over these other known prior art memory systems.